> ## Content Index
> Fetch the complete content index at: https://cms.yufeiran.com/llms.txt
> Use this file to discover other available public pages before exploring further.

# SPI Flash Read Module [Verilog]
- URL: https://cms.yufeiran.com/en-spi-flash-du-qu-mo-kuai/
- Published: 2021-03-04T00:22:52.000Z
- Updated: 2026-10-05T14:57:37.000Z
- Author: Feiran Yu
- Tags: works, #lang-en, #legacy-import

## Requirement Analysis

This module implements a Flash controller that reads 4 bytes at a time.

As mentioned in [Building a Computer with Nexys4 DDR \[1\]: Hardware](https://yufeiran.com/en/yong-nexys4ddr-zhi-zuo-yi-tai-ji-suan-ji-1/?ref=cms.yufeiran.com), the computer needs a “hard disk” for reading read-only data.

## Principle Analysis

The SPI Flash chip used by Nexys4 DDR is the S25FL128S.

**The circuit diagram is below:**

![pic 1](https://yufeiran.com/content/images/2021/03/QQ--20210304162150.png)

### What Is SPI?

For simplicity, I only introduce the basics here. For details, see the [wiki](https://zh.wikipedia.org/wiki/%E5%BA%8F%E5%88%97%E5%91%A8%E9%82%8A%E4%BB%8B%E9%9D%A2?ref=cms.yufeiran.com).

SPI is a serial bus protocol. Data is transmitted bit by bit through a wire. The signals needed here are `sck`, `cs_n`, `si`, and `so`.

`sck` is the clock signal, used for synchronization. Its frequency can be chosen freely within the working range.

`cs_n` is the chip-select signal. The `_n` suffix means active low, so the chip starts working when `cs_n` is pulled low.

`si` is the signal line input to the master device. Reading data from the Flash chip depends on it.

`so` is the signal line input to the Flash chip. Writing data to the Flash chip depends on it.

### What Is a Flash Chip?

Simply put, it consists of many readable and writable cells, [EEPROM](https://zh.wikipedia.org/wiki/%E9%9B%BB%E5%AD%90%E6%8A%B9%E9%99%A4%E5%BC%8F%E5%8F%AF%E8%A4%87%E5%AF%AB%E5%94%AF%E8%AE%80%E8%A8%98%E6%86%B6%E9%AB%94?ref=cms.yufeiran.com), plus a [controller](https://zh.wikipedia.org/wiki/%E9%97%AA%E5%AD%98%E6%8E%A7%E5%88%B6%E5%99%A8?ref=cms.yufeiran.com). The controller wraps many commands for operating those cells. So the most important part of using a Flash chip is sending the correct commands to its controller.

The structure of the Flash chip is shown below:

![pic 2](https://yufeiran.com/content/images/2021/03/QQ--20210304164500.png)

Flash commands vary slightly across manufacturers, but because there are standards, most common commands are the same. You can refer to each chip’s documentation.

[S25FL128S chip documentation](https://www.cypress.com/file/448601/download?ref=cms.yufeiran.com)

### Timing

#### Flash Chip Timing

Since we only need to read data, this article only introduces the one command used here: `READ`.

According to the S25FL128S documentation, the timing of the read command is:

![pic 3](https://yufeiran.com/content/images/2021/03/QQ--20210304165224.png)

From the diagram, to read data we need to:

1. Pull `cs_n` low.
2. Keep `sck` within the working frequency range. The datasheet says the maximum frequency for the `READ` command is 50 MHz, so `sck` can be anywhere in `(0, 50M]`. Since the onboard crystal of Nexys4 DDR is 100 MHz, 50 MHz is convenient to generate by division.

![pic 4](https://yufeiran.com/content/images/2021/03/QQ--20210304165930.png)

1. Send the `READ` command, `03H`, and the 24-bit address bit by bit through the `so` signal line.
2. Finally, the Flash chip outputs data bit by bit through the `si` signal line.

#### Wishbone Bus Read Timing

As a peripheral, the Flash controller needs to connect to the bus, so the interface must satisfy the bus requirements.

This computer uses the Wishbone bus. Its timing is relatively simple. Here is the signal flow for a bus read operation:

![pic 5](https://yufeiran.com/content/images/2021/03/QQ--20210305171717.png)

In short, during operation, `STB_O` and `CYC_O` are raised at the same time, the address is put into `ADR_O`, and then the circuit waits for clock cycles on `CLK_I`. The bus then waits for the peripheral. When the peripheral finishes processing the signal, it raises `ACK_I` to complete the transfer.

After the master receives the data, it lowers `STB_O` and `CYC_O`. At that point, the peripheral knows that the access is complete and lowers `ACK_I`.

## Design

### State Machine Design

This part mainly refers to [this article](https://blog.csdn.net/qimoDIY/article/details/86770745?ref=cms.yufeiran.com).

As shown below:

![pic 6](https://yufeiran.com/content/images/2021/03/-----.png)